The invention relates to a test circuit equipped with MOS transistors and accommodated on a single substrate together with at least one further MOS-circuit, which test circuit comprises one or more test terinals, which may be combined with terminals of the further circuit nd by means of which one or more test signals of a polarity opposite to that of the normal supply voltage can be applied, the further circuit then supplying monitoring signals which are indicative of the correst or incorrect operation of the further circuit, thereby enabling part or all of said further circuit to be tested.
As already stated in German Patent Application No. P 29 05 294.6, it is necessary, as the degree of integration and thus the complexity of integrated circuits increases, to test the integrated circuit during fabrication by so-called pre-testing and after fabrication by so-called final testing, in order to obtain better detection of any defects in fabrication.
However, as the degree of integration increases the number of external connections can not be increased to the same extent, so that it becomes more and more difficult to test such circuits. A test circuit which is designed to accept test signals of a polarity opposed to that of the normal supply voltage of the integrated circuit is known from German Patent Application No. P 29 05 294.6.
As a result of mismatches at the individual terminals of the IC, as is apparent from experimental results, it may happen that during normal operation of the circuit voltage transients of a polarity opposite to that of the normal supply voltage are produced, so that the test circuit in accordance with the previous Patent Application No. P 29 05 294.6 is turned on inadvertently during normal operation. It is obvious that such a changeover to the so-called test mode leads to incorrect operation of the circuitry during normal operation and may result in failure of the complete system in which such a device is included.